Verilog frontend integration

[fabianschuiki]

This is a draft on how we could add the Slang Verilog frontend to CIRCT and turn the AST it generates into a lower-level dialect that preserves all the Verilog intricacies.

The implementation is too simplistic to land in CIRCT as is, since it wouldn't be very useful. We'll have to figure out how much functionality we want to add (e.g. a lowering path to HW?) that would make the Slang frontend integration useful as a standalone thing to develop further.