[FIRRTL] Preserve 1D vector from MemToRegOfVec

[prithayan]

Add an attribute preserve_type to preserve the 1D register generated from MemToRegOfVec.

[uenoku]

Thanks! The change makes sense to me! One issue we have is that the current result of memory.fir is like this:

 always @(posedge clock) begin
    memory <= {{wEn & wMask & (&wAddr) ? wData : rwEn & rwMode & rwMask & (&rwAddr) ? rwDataIn :
                                memory[2'h3]}, {wEn & wMask & wAddr == 2'h2 ? wData : rwEn & rwMode & rwMask & rwAddr ==
                                2'h2 ? rwDataIn : memory[2'h2]}, {wEn & wMask & wAddr == 2'h1 ? wData : rwEn & rwMode &
                                rwMask & rwAddr == 2'h1 ? rwDataIn : memory[2'h1]}, {wEn & wMask & wAddr == 2'h0 ? wData :
                                rwEn & rwMode & rwMask & rwAddr == 2'h0 ? rwDataIn : memory[2'h0]}};
    addr <= rAddr;
  end // always @(posedge)

I think this is semantically correct; but we have to modify LowerSeqToSV to decompose the array in the rhs before landing this PR.

[uenoku]

I'm not sure making preserve_type attribute into ODS defined one is a good idea since that attribute is used by only LowerTypes :thinking:

[prithayan]

I'm not sure making preserve_type attribute into ODS defined one is a good idea since that attribute is used by only LowerTypes 🤔

I added it into the attribute list because we have to make sure any transformations like the InferResets copies the attribute while transforming the register into a reset register. Otherwise, we have to manually inspect and add the attribute. But its true that in this case, only 3 passes need to care about it, MemToRegOfVec, InferResets and LowerTypes.

[darthscsi]

Can we safely move the logic for MemToRegOfVec so it operates on seq.mem and leave memories unexpanded?

[prithayan]

Closing as this is no longer relevant.