[HW] Memory Lowering: Use Generated Op and Schema to lower FMemModuleOp

[prithayan]

This PR lowers the FMemModuleOp to HWModuleGeneratedOp and HWGeneratorSchemaOp instead of HWModuleExternOp. Also ensure the HWModuleGeneratedOp is lowered exactly as HWModuleExternOp in ExportVerilog.

This PR is an attempt to preserve the metadata required for memory macro replacement from the FIRRTL dialect, after LowerToHW. This should replace the requirement for embedding the memory metadata into verbatim Ops for json export.

All the attributes that are being embedded into the VerbatimOp in the CreateSifiveMetadata will be stored with the hw.generator.schema op, and the hw.module.generated stores the values for the corresponding attributes.

An example:

hw.generator.schema @FIRRTLSeqMemSchema, "FIRRTL_Seq_Memory", 
  ["depth", "numReadPorts", "numWritePorts", "numReadWritePorts", "readLatency", "writeLatency",
   "width", "maskGran", "extraPorts"]
hw.module.generated @SiFive_CCache_cc_dir_ext, @FIRRTLSeqMemSchema(%RW0_addr: i8, %RW0_en: i1, %RW0_clk: i1, %RW0_wmode: i1, %RW0_wdata: i216, %RW0_wmask: i8, %user_inputs: i8)
  ->  (RW0_rdata: i216) attributes 
    {depth = 256 : ui64, extraPorts = [{direction = "input", name = "user_inputs", width = 8 : ui32}],
     maskGran = 27 : ui32, numReadPorts = 0 : ui32, numReadWritePorts = 1 : ui32, numWritePorts = 0 : ui32,
     readLatency = 1 : ui32, verilogName = "SiFive_CCache_cc_dir_ext", width = 216 : ui32, writeLatency = 1 : ui32}

The mlir can now be queried by other tools like python, to get the required metadata instead of parsing the json.