Circular logic not detected

[Schottkyc137]

trafficstars

The following code:

module {
  hw.module @foo() -> (o: i1) {
    %0 = comb.parity %0 : i1
    hw.output %0 : i1
  }
}

is considered correct and produces the following Verilog output (using circt-opt circular.mlir --export-verilog):

module foo(	// circular.mlir:2:3
  output o);

  wire _GEN = ^_GEN;	// circular.mlir:3:10
  assign o = _GEN;	// circular.mlir:4:5
endmodule

analyzing this with Verilator gives the following error:

$ verilator circular.v --lint-only 
%Error: circular.v:5:13: Wire inputs its own output, creating circular logic (wire x=x)
    5 |   wire _GEN = ^_GEN;  
      |             ^
%Warning-UNOPTFLAT: circular.v:5:8: Signal unoptimizable: Feedback to clock or circular logic: 'foo._GEN'
    5 |   wire _GEN = ^_GEN;  
      |        ^~~~
                    ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=4.222
                    ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
                    circular.v:5:8:      Example path: foo._GEN
                    circular.v:5:13:      Example path: ASSIGNW
                    circular.v:5:8:      Example path: foo._GEN
%Error: Exiting due to 1 error(s), 1 warning(s)

in other words, this simple circular logic is not detected by the tools.

On a side note: firtool seems to hang up on this simple example and other circular examples

[uenoku]

On a side note: firtool seems to hang up on this simple example and other circular examples

Thanks, it seems PrettifyVerilog is hanging up at https://github.com/llvm/circt/blob/141eae7157eada07b3baf350935b984b50a715da/lib/Dialect/SV/Transforms/PrettifyVerilog.cpp#L140 because of the circular use.

I think circular logic is allowed by design to represent flip-flop etc but I agree that it would be nice to raise errors for this kind of obviously invalid circuits.