[ExportVerilog] Weird wire/assign statement indent

[uenoku]

I haven't reduced yet but I have often seen indent around wire/assign broken. For example, in DivSqrtRecF64_mulAddZ31 module in FPU.fir compiled with firtool -drop-names, there is code like this:

      wire _T_275 = valid_PA & valid_leaving_PA;        // DivSqrtRecF64_mulAddZ31.scala:233:55, :283:28
  assign _T_278 = ~valid_PA | valid_leaving_PA; // DivSqrtRecF64_mulAddZ31.scala:233:55, :235:36, :284:28
      wire _T_298 = specialCodeB_PB[2:1] != 2'h3;       // DivSqrtRecF64_mulAddZ31.scala:97:30, :212:46, :293:24, :298:25, :311:{41,48}

[dtzSiFive]

Is this still an issue? Drop names is enabled by default now, but I can't reproduce with the linked FPU.fir.

[dtzSiFive]

Don't see this behavior anymore, please re-open if still a problem or should be looked into.