circt
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llvm
Circuit IR Compilers and Tools
This PR switches ExportVerilog emission mode to new simplified version by default. `useOldEmissionMode` flag is added to use the old emission mode. If there is no problem for a few...
* [D131702](https://reviews.llvm.org/D131702) changed segment size attributes * [D131537](https://reviews.llvm.org/D131537) modernized LLVM ops
While trying to use the Mac firtool pre-built binary on a larger design I noticed that it sometimes throws bogus errors, for example saying that a value is not fully...
This can be used to load HW modules from an MLIR file on disk, and insert them into a fresh System.
This PR introduces two operations to handle `RefType`. The `RefType` can be used to represent dataflow across modules and only module/instance ports can declare values of `RefType`. The following operations...
Currently an HW array that only consists of constants is lowered in the same way as an array containing dynamic arrays: by creating the array at runtime and allocating it...
automatic logic can be circumvented by passing `--lowering-options=disallowLocalVariables` during `--export-verilog`. For PyCDE, We'd want to be able to - at some point in the stack - to specify this variable....
```mlir firrtl.circuit "Example" { firrtl.module private @Test(in %in1: !firrtl.uint, in %in2: !firrtl.uint, in %clock: !firrtl.clock, out %out: !firrtl.uint) { %r = firrtl.reg %clock : !firrtl.uint %0 = firrtl.or %in1, %r...
This issue intends to track the progress on completing the [handshake-to-hw lowering](https://github.com/llvm/circt/blob/main/include/circt/Conversion/HandshakeToHW.h), and by doing so, transition off of our current [FIRRTL-based lowering path](https://github.com/llvm/circt/blob/main/include/circt/Conversion/HandshakeToFIRRTL.h). The * [x] implement top-level lowering...