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util: Add barriers support for MIPS

Open matoro opened this issue 3 years ago • 1 comments

MIPS has the capability to issue memory barriers. Implement this using a full (heavy) barrier. This is the only variant that is guaranteed to exist on all hardware. Other barriers are only available on mipsr6 or some special earlier implementations. However even on the former the kernel uses a full barrier for safety due to not yet trusting their reliability.

See: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=881731 See: https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00605-2B-CMPCOHERE-AFP-01.01.pdf See: https://github.com/torvalds/linux/blob/master/arch/mips/include/asm/sync.h

matoro avatar Sep 16 '22 20:09 matoro

@jgunthorpe ???

rleon avatar Sep 21 '22 09:09 rleon

mips may have memory barriers, but do any DMA cache coherent MIPS implementations exist? Which ones are they?

jgunthorpe avatar Sep 26 '22 17:09 jgunthorpe

mips may have memory barriers, but do any DMA cache coherent MIPS implementations exist? Which ones are they?

Yes, seems to be everything that doesn't select DMA_NONCOHERENT. A lot of boards select this in arch/mips/Kconfig but not all. My Octeon II is not one of them:

$ zgrep -i "coherent" /proc/config.gz
CONFIG_DMA_DECLARE_COHERENT=y

Is this correct, or is there a better way to determine this?

matoro avatar Sep 26 '22 18:09 matoro