Guanxi Lu

1. Allow passing `port_width` attribute of partitions in `GenerateNetwork`, corresponding to the updates in HLS implementation. 2. Fix typos in simple end-to-end tutorial 3. For examples, `port_width` is still set...

1. Implementation to allow passing `port_width` 2. Implementation to allow passing `DMA_WIDTH` and `DATA_WIDTH` 3. Implementation to reformat `common.hpp` and `common_tb.hpp` header files 4. Fix data overlap issues in `mem_write`...

In fpgaConvNet, [`Gemm layer`](https://onnx.ai/onnx/operators/onnx__Gemm.html#gemm-7) is implemented as [`InnerProductLayer`](https://github.com/AlexMontgomerie/fpgaconvnet-model/blob/main/fpgaconvnet/models/layers/InnerProductLayer.py#L13). However, the main difference is that Gemm layer supports more parameters (Boolean flags `transA`, `transB`, scalars `alpha`, `beta`). For the current model,...