Lenny Truong

Non determinism in verilog backend

4

```bash cd coreir git checkout determinism make clean make install -j pip install delegator.py pytest while pytest tests/binary/test_concat.py; do :; done # should eventually fail ``` Contents of test_concat.py ```python...

Logging Infrastructure

7

I'd like to add some logging infrastructure so we can more easily develop/debug with something more flexible than using `std::cout` and comments. My initial search reveals: https://github.com/gabime/spdlog as a header...

Here's a harmless case where inlining the primitives doesn't quite work as well as it should. Ideally the intermediate wire is not generated for the constant (but at least the...

Should only descend into tuple/array if there's a nested clock type, otherwise skip (avoids lazy children elaboration when possible).

Smart when lazy

3

Updates the array2 logic to properly handle conditionally driven values. The main change requires that we ensure that children are "rewired" based on the conditionally driven information of the parent....

[Primitives] Fix slice primitives

2

* Promote int-like values in get_slice/set_slice * Update doc to refer to set_index instead of set_bit * Support set_slice of length 1 for constant values

[InlineVerilog] Wire inlining produces bad Verilog when using `ifdef`

2

Simple example: ```python import magma as m class Foo(m.Circuit): io = m.IO(I=m.In(m.Bits[32]), O=m.Out(m.Bit)) m.inline_verilog("`ifdef LOGGING_ON") m.inline_verilog("$display(\"%x\", {io.I[0]});") m.inline_verilog("`endif LOGGING_ON") io.O @= io.I[0] m.compile("build/Foo", Foo, output="mlir-verilog") ``` produces ```verilog // Generated...

```python import magma as m class Foo(m.Circuit): io = m.IO(I=m.In(m.SInt[2]), S=m.In(m.Bit), O=m.Out(m.SInt[2])) with m.when(io.S): io.O @= io.I with m.otherwise(): io.O @= m.sint(m.uint(io.I) >> 1) m.compile("build/Foo", Foo, output="mlir-verilog") ``` produces ```verilog...

Feature request: Using halidetuner with multiple inputs

1

I have a Halide program I'd like to autotune using the `halidetuner.py` example. Would it be possible to extend it to support multiple inputs of different sizes? Currently it seems...

Update internal signal poking for MLIR

1

The hack to poke an internal verilog signal corresponding to a coreir register no longer works: https://github.com/leonardt/fault/blob/master/fault/wrapper.py#L141-L147 Need to refer to the generated MLIR name (could insert a name in...