lekcyjna123
lekcyjna123
It would be nice to have a benchmarks results for each part (submodule/connected component) which run in one cycle, so that we will know which modules are the biggest and...
Having `verify_branch` in precommit cause a big delay in handling branches, because we wait till retirement to restore instruction fetching. Please optimise this.
Today I am trying to introduce not backward compatible changes in layouts on main pipeline (change register id to tuple with register id and register type). Changes in production code...
We would like to use pipelining as much as possible, so it would be nice to use #410 and check if we can optimise some modules (e.g. FU's) to be...
In one of open source cores FreeRF is implemented as array of bits. It would be good to implement it in coreblocks and compare costs.
As for now ROB is implemented using array of registers. It would be good to use memory, to reduce ROB cost.
As for now our wakeup-select logic is very simply (take the last ready instruction - last in sense of index of RS), so in future it would be great to...
Compare ideas for instruction decoding: - lookup table to assign OpType - generating tree with "if" to choose maximum subpart which allow to assign proper OpType
As we have seen in [comment](https://github.com/kuznia-rdzeni/coreblocks/pull/379#issuecomment-1574332711). Decoder can have a great impact on whole core results. On the one side it has a lot of combinational paths which can lower...
When we switch scheduler in transaction core from eager deterministic to trivial round robin (I have done that by changing default in definition of TransactionManager) then test `test_1_way (test.frontend.test_icache.TestICache_0_blk_size16B_rv32i)` stuck...