Aled Cuda

From a prelim glance I like @jorolf proposed interface better than mine, some notes follow below: > * AXI3 and AXI5 specific signals are missing, but could be added easily...

Ok I've taken the proposed interface for a spin (and forced an unsuspecting undergrad to make an AXI peripheral as well): 1. Having the properties distinct from the signature feels...

An alternative approach I considered was adjusting [this](https://github.com/Xilinx/PYNQ/blob/de6b6fc3a803945d59f8f06523addfe0d9b60a1c/pynq/pl_server/embedded_device.py#L563) to check for the name "PSDDR" instead of the address zero and including `.xclbin` file along the bitstream, but that felt like...

Yeah that's what I assumed, I've tested the change on our 4x2, will give it a test on our ZCU111

I've tested this on our ZCU111 and RFSoC4x2 and it appears to work on both; Is there anything we can do to help get this functionality or something equivalent to...