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Published 20 hours ago • verified publisher icon lakshmi-sathi

Resources for chip design using efabless caravel

Open GitDiscipline opened this issue 2 years ago • 0 comments

Hi, could you please provide any other resources other than that of efabless caravel user project documentation for chip design using caravel that led to the succesful deployment of your PLL ?

GitDiscipline avatar Feb 15 '22 11:02 GitDiscipline