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ISTR that while SHA256 signing works, an issue remained with 2048 bit RSA keys.

@AdriaoNeves added support for 4096 and 3072 bit keys with commits ce71b17, dbe9321 and 366adbd, so perhaps 2048 bit keys are supported now as well? @ejpir, could you retry with...

Digging out this ancient but still relevant issue: It would indeed by useful if the initial GPIO polarity could be defined in the HAT EEPROM. Obviously, this only applies if...

Setting the polarity and/or drive in the HAT EEPROM won't prevent this, only reduce the interval for which the CS line appears to be asserted. Is that going to be...

Okay, so the recommendation is to set these GPIOs to inputs in the HAT EEPROM with an appropriate pull, which may be augmented with an external pull. Understood. Actually that's...

The struct spi_ioc_transfer passed in from user space contains `delay_usecs` and `word_delay_usecs` attributes. First thing to check is whether these are non-zero. E.g. if your code is written in C...

Is that a delay of 3 usec or 3 msec between CS assert and first clock tick? If the former, I'm afraid that may be as good as it gets...

@Jephinus: When your program invokes the `SPI_IOC_MESSAGE` ioctl, it eventually ends up in spi_transfer_one_message(). The function calls `spi_set_cs()` to assert Chip Select, then iterates over the transfers in the message...

I've hacked together a patch which caches the last-used clock speed and avoids setting it upon every SPI transfer if the current transfer's clock speed is the same as the...

@P33M The patch you've linked to makes enumeration work reliably with the ASMedia ASM1184e, but timeouts (and thus kernel panics) persist with the Pericom PI7C9X2G404SL (occasionally) and with the Pericom...