read performs 2 access cycles

[jeras]

I tested this code on a FPGA board and observed 2 access cycles on the system bus. The two access cycles are very close one after another, from which i would deduce, they are executed by the same C code. If the two accesses were requested by separate lines of Python code, I would expect to see a longer pause between the two.

[florisla]

Can you provide more background information? Which board are you using, what is the OS where you run Python?

[jeras]

This was on a Xilinx UltraScale+ MPSoC board running Petalinux, and I observed the accesses using ILA. I am not working on the same project anymore, so I am unable to reproduce the issue.