ROB flushing rework for interrupt and exception handling

[Kristopher38]

Xiangshan realizes its ROB flushing in a single cycle by rolling back pointers in the ROB and Free-RF-FIFO and we should do the same. Taken from the discussion in #254:

if we allocate a physical register for each instruction even if it doesn't need one, we get RF FIFO recovery (and by extension ROB flushing) for free (XiangShan - autotranslation with some of my creative writing to make it easier to digest):

At present, FreeList has two implementations in Xiangshan, which are used when reference counting is/isn't enabled. For the case where there is no reference counting, when ROB rollback occurs, the registers that need to be put back into the FreeList must be the ones that were just allocated for the ROB entries, and the number of physical registers that need to be released in a rollback is the same as the number of ROB entries to be flushed. In this case, the FreeList does not need to be written to repeatedly in a multicycle fashion, only the dequeuing FIFO pointer needs to be rolled back forward.

Comment on the last sentence - this is safe since we have as many FIFO slots as there are physical registers so the data that was there before we moved the dequeuing pointer further will still be there when we roll it back :)