Kaleb Barrett

I have a shot in the dark for you. 1. The test fails 2. The regression manager calls `tear_down` 3. which calls `simulator.stop_simulator` 4. which calls `gpi_sim_end` 5. which calls...

>I never see this method entered: `VpiImpl::sim_end` >`registered_impls[0]->sim_end();` These are one in the same. More than likely the prints in `sim_end` are simply not flushing. `vpiControl(vpiFinish)` in `VpiImpl::sim_end` do not...

Also, if calling `vpiFinish` runs the shutdown callback immediately, `Py_Finalize` *is* called, is the stack destroyed at that point? Does the stack unravel causing `Py_BuildValue` in `stop_simulator` fail? No doubt...

@markmelvin The line in question should not need to be conditioned. It's worth investigating why it is in your case, and fix that issue instead.

I would say that it starts out life `NULL` because it's a .bss variable, and never gets set if `register_embed` is never run. But nothing would work if that were...

It does not have to do with underscores. It cannot find `dut.asc_gen[20]`. It can find the `dut.asc_gen` pseudo-region. After looking a bit harder I noticed that it seems like the...

One more "feature" I'd like to take into account in the refactor is black-boxing test discovery, so we can experiment with a more pytest-like test discovery in the future. Segregating...

So I found a way forward with the decoupling. It involves removing all references to tests from the scheduler and injecting behavior into the scheduler that decides when to end...

What is the error? I don't have Xcelium available to me to test this. Is this breaking for other simulators?

If you have both Verilog and VHDL sources, you have to tie break. Below is the logic. It only deduces VHDL or Verilog if the opposite `SOURCES` variable is empty...