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Open kosarev opened this issue 3 years ago • 3 comments

Aside of #2, this seems to be the only missing feature.

kosarev avatar Oct 17 '20 07:10 kosarev

Rather than asserting, could the default implementation behave as though FF is read from the bus to give RST &38? From what I remember from testing IM 0 and IM 1 behave the same if there's nothing providing an instruction on the bus. The timing might be 6T instead of 7T for ack.

simonowen avatar Jun 02 '21 15:06 simonowen

Certainly a good idea. 9ae1dad should implement it. Regarding timings: according to my copy of the Sean Young paper, IM 0 and IM 1 both take 13 ticks, which I understand means we have ack(7) write(3) write(3) here.

kosarev avatar Jun 02 '21 18:06 kosarev

Now that the assert() is removed, this looks more like an enhancement rather than a bug.

kosarev avatar Jun 03 '21 09:06 kosarev