Karol Gugala

@ktemkin did you have a chance to take a look at this?

looks like `nmigen-stdio` was missing in my setup. The build process was actually showing that in the log, but did not stop on missing dependency. This ended up with empty...

hi @Talha-Ahmed-1 can you link to the design you're trying to build?

we need the following: - [x] Vivado - [x] Yosys + Vivado (PnR) - [x] Yosys + Arachne - [x] Yosys + NextPnR - [x] Yosys + VPR - [...

Hi @p-owens, you need to do a few things here: 1. Configure the FVDMA to accept AXI Stream on the input 2. Have the Full AXI/or Wishbone bus connected to...

I'm all for `yosys-chipsalliance-plugins`

python SDF parser being developed in https://github.com/SymbiFlow/python-sdf-timing SDF producer is a part of this PR https://github.com/SymbiFlow/prjxray/pull/706 GitHubSymbiFlow/python-sdf-timingPython library for working Standard Delay Format (SDF) Timing Annotation files. - SymbiFlow/python-sdf-timing

The tool is more or less ready. I'm pretty sure it has bugs, and does not handle all the SDF spec. Will fix the bugs as they appear in testing.

The license is there, it looks like the Vivado version available in the CI does not support the part. I'm updating the tool. Once this is done I'll restart the...

@hansfbaier I've bumped the tools and landed https://github.com/f4pga/prjxray/pull/1918. This PR has to be rebased on top of that to be able to use updated tool and access the license server....