Karol Gugala

so the `vpr_pbtype_to_eblif` looks for leafs only https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/utils/vpr_pbtype_to_eblif.py#L83 and generates the eblif from that one. The `find_leaf` function returns only leaf pb_types (the ones having eblif tag defined) https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/utils/lib/pb_type.py#L22 So...

It looks like we can handle the cases where the top module is not a blackbox with Yosys - we can generate the test blif from verilog. I did some...

@googlebot I consent.

I have rebased this and resolved conflicts. @proppy can we land this?

the functionality is in place, we can access the license server from a CI (including PRs). I've restarted CI here (it was red due to a random failure)

Oh, I have to sign-off commits

I've rebased the PR. Once the CI is green we can land it

actually we have some initial support for generating partial bitstreams here https://github.com/antmicro/prjxray/tree/partial-bitstream-support. We'll open a PR to mainline soon GitHubantmicro/prjxrayDocumenting the Xilinx 7-series bit-stream format. - antmicro/prjxray

> @kgugala I was sure we had a bug about this previously? We had, but back then DSP timings fuzzing was disabled. I'll take a look on this (or get...

I cannot reproduce this one with the latest code @mithro is it still happening in kokoro builds?