KC Sivaramakrishnan

Thanks everyone for the comments. I've squashed the commit history and added a Changes entry. This PR is ready to merge. As future work, we need the following: 1. Include...

> Also, bonus points for a backtrace of where the perform happened, as happens with exceptions when CAMLRUNPARAM=b. This is already done as unhandled effects raise `Unhandled` exception at the...

Thanks for the PR @nojb. It will likely take me 2 weeks before I can start reviewing. Busy with teaching. Hope that's ok. @ctk21 would also be a good person...

Hi @nojb, this is next on my list.

I've started reviewing the PR (finally). I have managed to build the branch on `riscv64/ubuntu` docker image. The testsuite is currently running. Given the comprehensive nature of the effect handler...

There is some discrepancy between compilation of the memory model mentioned in the original PR message and the implementation. The compilation mentioned in the original PR message is not completely...

The _atomic_ load also can be simplified a bit. ## Atomic load Currently, the atomic load is ``` fence iorw, iorw ld fence iorw, iorw ``` If you look at...

Agree with extending `cpu_relax` with RISC-V `PAUSE` instruction.

This looks reasonable to me. Given that remarking is rare, this queue could just be a lock-protected linked list, couldn't it? How does work end up in the global remark...

Ok. Global remark queue sounds reasonable.