Kareem Farid

Fixes #275

Point to the report file of Checker.YosysSynthChecks

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### Description `Checker.YosysSynthChecks` reports errors on `synthesis__check_error__count`. However, there is nothing pointing towards the errors themselves and where are they located. ### Proposal Point to the report file relating to...

Powerswitch floorplanning and placement issues

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### Describe the bug I am unable to insert power switches using UPF without causing overlaps. I am using the power switch abstract view that is present in the test...

* Script was trying to fetch values from wrong paths. Paths are corrected to nom corner. These are the fixed metrics: - Power values - `critical_path_report` - some wns and...

Incorrect Makefile recipe dependencies

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https://github.com/efabless/caravel_user_project/blob/a01f3f0ece3c835d8788c87212006236e2167d7f/openlane/Makefile#L87-L89 This uses venv assuming venv is installed with volare inside. The recipe should have a dependency responsible for installing venv and volare.

Remove default_nettype statements at the end of the RTL

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Surfaced by https://github.com/The-OpenROAD-Project/OpenLane/issues/2083. Yosys would use the `default nettype wire` when compiling the user project. Although this might be an ambiguity in yosys behavior, I don't see the need of...

Add option to stream out GDS with subcut layer

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### Description Title ### Proposal Add a Magic step to do that

Clock Propagation Changes

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* `OpenROAD.*STA*`: * Don't set propagated clock outside of the sdc * Move set propagated clock inside the default sdc file * Add backwards compatible behavior to use set propagated...

### Description Title ### Proposal Title

Add new metrics

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Metrics: * Add: * `design__instance__count__total` * `design__instance__count__welltap` * `design__instance__count__decap` * `design__instance__count__fill` * `design__instance__count__diode` `openlane.steps.openroad`: * Add new metrics for cells counts for the following steps * `OpenROAD.Floorplan` * `OpenROAD.ResizerTimingPostCTS` *...