Kareem Farid
Kareem Farid
@mattvenn Also I believe yosys passed because of this https://github.com/mattvenn/caravel_user_project_mpw9e/blob/a2d1a4b8a3d980b9a5e843b9922fc98e9ef70ba7/verilog/rtl/user_project_wrapper.v#L104C1-L105C22 - Making it accept implicitly declared wires. Probably related to this issue in yosys https://github.com/YosysHQ/yosys/issues/1217
@mattvenn Perhaps you could open an issue in the example repo.
The reproducible isn't working for some reason, looking into it. Meanwhile, can you upload your source files and config?
The source of the issue is including `gf180mcu_fd_io.v` in the design input verilog sources files. By uploading the source files, I wanted to know whether this was absolutely needed and...
The log file will reference signal that is being resized. You should update your RTL accordingly.
@yslim2002 The google colab in the zip file clones this repo https://github.com/VenciFreeman/FFT_ChipDesign. I am assuming this contains the source verilog files. In the section of the log file that you...
I am not aware of a way to show _all_ paths. Would that really be useful ? There is room for improvement here were we can parameterize `-group_count` and use...
Close this as stale.
With the default configuration, vertical met4 stripes have a high pitch. There is no vertical met4 stripe that is passing through the macro. This is the cause of your LVS...
> Thank you for looking into the issue. VDD is there as a floating pin, to fulfill pdn_macro_hooks pins and nets requirements. I have confirmed it has connected on my...