jzbydniewski

Looking at stack traces, I can see that it's always one of registers (r0 usually, might depend on debug changes introduced) that contains invalid value. Could it be that there...

I added the following change to the tcp_check_space to catch the issue earlier: ``` diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c index fd9067062f2a..0152a30bfc35 100644 --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c @@ -5463,6 +5463,12 @@ void...

Here is yet another reproduction, SmaRT: [smart-log-core-1.txt](https://github.com/foss-for-synopsys-dwc-arc-processors/linux/files/15307580/smart-log-core-1.txt) [smart-log-core-2.txt](https://github.com/foss-for-synopsys-dwc-arc-processors/linux/files/15307581/smart-log-core-2.txt) [smart-log-core-3.txt](https://github.com/foss-for-synopsys-dwc-arc-processors/linux/files/15307582/smart-log-core-3.txt) 

Another reproduction, now I can see SmaRT looks matching with call stack, here is my analysis of the situation  From what I see content of registers r16..r24 looks matching...

@xxkent I tried with this patch but it's the same  Do I understand correctly that SmaRT is showing full trace of instructions executed by a particular CPU (even if...

Contents of dcache for each core + L2 cache: [dcache-core1.txt](https://github.com/foss-for-synopsys-dwc-arc-processors/linux/files/15321449/dcache-core1.txt) [dcache-core2.txt](https://github.com/foss-for-synopsys-dwc-arc-processors/linux/files/15321450/dcache-core2.txt) [dcache-core3.txt](https://github.com/foss-for-synopsys-dwc-arc-processors/linux/files/15321451/dcache-core3.txt) [l2-cache.txt](https://github.com/foss-for-synopsys-dwc-arc-processors/linux/files/15321453/l2-cache.txt)  According to the contents of data cache for core 1 where the issue triggered, the ldd.ab...

I'm testing now with kernel option CONFIG_ARC_HAS_LL64=n. No reproduction within 3 days. Buildroot didn't require change as it's not passing "mll64" to gcc, and from what I see by default...

This is what I see with -off=flush_dcache  it looks like the value that should have been loaded to r14 (at address 0x81c35cbc) is in L1 data cache line marked...

The good news is that with patch https://github.com/foss-for-synopsys-dwc-arc-processors/linux/commit/28e6344920c628041a9447472dbf1ce3c2c5834f I no longer can see boot-time freeze, tried over 2k times.

> Could you provide call stacks for each core from MDB? Yes, here new capture of SmaRT + call stacks for each core: [callstack-core0.txt](https://github.com/foss-for-synopsys-dwc-arc-processors/linux/files/15259297/callstack-core0.txt) [callstack-core1.txt](https://github.com/foss-for-synopsys-dwc-arc-processors/linux/files/15259299/callstack-core1.txt) [callstack-core2.txt](https://github.com/foss-for-synopsys-dwc-arc-processors/linux/files/15259300/callstack-core2.txt) [smart-core0.txt](https://github.com/foss-for-synopsys-dwc-arc-processors/linux/files/15259302/smart-core0.txt) [smart-core1.txt](https://github.com/foss-for-synopsys-dwc-arc-processors/linux/files/15259303/smart-core1.txt) [smart-core2.txt](https://github.com/foss-for-synopsys-dwc-arc-processors/linux/files/15259304/smart-core2.txt) This...