simple sdc file added to see some timing violation

[infphyny]

Gowin ide seem unable to calculate properly all timings because there is no timing paths to get frequency of hdmi_clk_5x . Gowin documentation section 5.1.3 (see notes) recommend to add complete timing constraint to the design.

The constraint I added is from port clk to the output registers of tmds_encoder module.

module tmds_encoder(
  input i_hdmi_clk,         // HDMI pixel clock
  input i_reset,            // reset (active high)
  input [7:0] i_data,       // Input 8-bit color
  input [1:0] i_ctrl,       // control data (vsync and hsync)
  input i_display_enable,   // high=pixel data active. low=display is in blanking area
  output reg [9:0] o_tmds   // encoded 10-bit TMDS data
);

Then I see violation in Setup Paths Table in Timing Analys Report.