Jessica Clarke

Stefan is a long-standing member of the community whose name features in multiple specifications

> > However, I do not expect that this requires changing the split of the CHERI extensions. Wouldn't it be sufficient to simply add clarifications to the current spec as...

Well, the question is whether it’s about accessing state, per the name, or system control as a whole (note that Arm take it to be the latter in Morello and...

I don't think it's useful to spend too much time looking at something as boring as SBI until the ISA is more nailed down. At the end of the day...

> So software for a purecap only core must not be relying on the state of that bit. That doesn't work; if the bit exists it needs to be set...

That requirement was deliberately dropped during the development of this spec (the CHERI spec enforces it) because people wanted tokens.

28 is correct, since `sigjmp_buf` is the same as `jmp_buf`, yet needs the extra 2 words. Similarly 40 for riscv32 (12 xlen + 12 flen + 2 xlen + extra...

Also, if you're trying to invalidate a read-only page whose accessed bit is clear on hardware that relies on software A+D emulation, the fact that you get a _store/AMO_ fault...

So, whilst in practice there may not be a security justification for mandating PTEs be writeable, I strongly believe that that relaxation makes it a complete nightmare to have any...

Not checking and not changing sounds terrifying...