jrrk

The driver you need is now incorporated into Vivado, follow the instructions on our website to install it if the sys Administator hasn’t done so already.

If you are working on an old version of LowRISC and Vivado, you can most likely use the latest adept install though we have not tried it.

It's not a good idea to change the address of the built-in peripherals, they are on a TileLink bus and there are many built-in assumptions in software and so on...

The boot.c/hello.c procedure mentioned earlier is not quite the first code executed. The Rocket hardware description contains an extra piece of code called ROMSlave, the sole purpose of which is...

The bottom inside the rocket is still used to provide memory map information. There is no need to adjust the reset vector for gdb use, it automatically sets the PC...

See below Sent from my iPhone > On 26 Feb 2018, at 22:58, sherrbc1 wrote: > >  > Per the 1.91 Privileged Specification, I found that the behavior of...

I haven’t investigated the AC701 board at all. The kc705_update branch was created explicitly for the KC705 and has no relevance to other boards (except as an exemplar of what...

The main problem is the DDR interface, there will be a limited choice of frequencies supported by MIG, this will feed into the AXI controller to DDR ratio, and consequently...

Dear Clare, The interface to the DDR on LowRISC is 16-bits (if you are talking about the Nexys4-DDR implementation). The DDR interface IP from Xilinx certainly supports a wider word...

It just so happens that the block ram in the FPGA build is 128 bits. So it should be very easy to interface this to your new design. It will...