s18: VDP/S16 graphics layer priority

[gyurco]

The VDP/S16 rgb output is mixed by an analogue switch. The mixing is controlled by the 315-5373 custom chip.

The PLD content translated to Verilog:

vdp_sel = vdp_en & vsp_ysn & (!vid16_en
    | (vdp_prio[2] & vdp_prio[1] & vdp_prio[0])  // 7
    | (tilemap[1] & vdp_prio[2] & vdp_prio[1])   // 6,7
    | (tilemap[4] & vdp_prio[2] & vdp_prio[1])   // 6,7
    | (obj_prio[0] & tilemap[1] & vdp_prio[2])   // 4,5,6,7
    | (obj_prio[0] & tilemap[4] & vdp_prio[2])   // 4,5,6,7
    | (!obj_prio[1] & vdp_prio[2] & vdp_prio[1]) // 6,7
    | (!tilemap[0] & vdp_prio[2] & vdp_prio[1])  // 6,7
    | (obj_prio[0] & tilemap[3] & tilemap[1] & vdp_prio[1]) // 2,3,6,7
    | (obj_prio[0] & tilemap[3] & tilemap[4] & vdp_prio[1]) // 2,3,6,7
    | (obj_prio[0] & !obj_prio[1] & vdp_prio[2] & vdp_prio[0]) // 5,7
    | (obj_prio[0] & tilemap[3] & tilemap[2] & tilemap[1]) // all
    | (obj_prio[0] & tilemap[3] & tilemap[2] & tilemap[4]) // all
    | (obj_prio[0] & !tilemap[0]& vdp_prio[2]) // 4,5,6,7
    | (obj_prio[0] & tilemap[3] & !obj_prio[1] & !tilemap[0] & vdp_prio[1]) // 2,3,6,7
    | (obj_prio[0] & tilemap[3] & !tilemap[0] & vdp_prio[1] & vdp_prio[0]) // 3,7
    | (obj_prio[0] & tilemap[3] & tilemap[2] & !obj_prio[1] & !tilemap[0])); // all