<ARM Architecture Reference Manual ARMv8> Note

[jmpews]

Prologue

RTFM!!!

abbr.

VMSA == Virtual Memory System Architecture MMU == Memory Management Unit VAs == virtual addresses PAs == physical addresses TLB == Translation Lookaside Buffer

The AArch64 Application Level Memory Model

Memory type overview

B2.1.2 General behavior of the caches

• An unlocked entry in a cache might not remain in that cache. The architecture does not guarantee that an unlocked cache entry remains in the cache or remains incoherent with the rest of memory.
• A locked entry in a cache is guaranteed to remain in that cache. The architecture does not guarantee that a locked cache entry remains incoherent with the rest of memory, that is, it might not remain dirty.
• It is guaranteed that no memory location that does not have a Normal Cacheable attribute is allocated into the cache.

B2.4.2 Memory hierarchy

B2.4.3 Application level access to functionality related to caches

SCTLR_EL1
https://github.com/xdtianyu/android-8.0.0_r4/blob/841bd21e187dd12d768a1fabc70b7e3c62beb339/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm

The AArch64 System Level Programmers' Model

Exception levels

• EL0 to EL3
• EL2 provides support for virtualization of Non-secure operation.
• EL3 provides support for switching between two Security states, Secure state and Non-secure state.
• An implementation might not include all of the Exception levels. All implementations must include EL0 and EL1. EL2 and EL3 are optional.
• When executing in AArch64 state, execution can move between Exception levels only on taking an exception or on returning from an exception:
• On taking an exception, the Exception level can only increase or remain the same.
• On returning from an exception, the Exception level can only decrease or remain the same.
• ELn 可以访问 ELm(m <= n) 的资源.

D3.4 Cache support

D3.4.7 About cache maintenance in AArch64 state

Typical Exception level usage model

EL0 Applications.
EL1 OS kernel and associated functions that are typically described as privileged.
EL2 Hypervisor.
EL3 Secure monitor.

The AArch64 Virtual Memory System Architecture