John Kressel

Aarch32 instructions are now handled in the A32 and T32 scanners.

Aarch64 ARM v8.2 instructions are handled in the A64 scanner.

This pull request adds handling for v8.1 instructions in both aarch32 and aarch64.

This commit adds IHL via the function riscv_inline_hash_lookup(). BRANCH_FSPACE has been increased to accommodate IHL. Additionally, free space checks have been added to register jump instructions handled in the scanner.

On both QEMU and the SiFive Unmatched these cases need to be covered otherwise MAMBO fails to run correctly.

RISC-V api helpers

3

Port some API helper functions to RISC-V

Various API helper functions ported to RISC-V, along with callback support and branch printing plugins

4

I have included the increased size of BRANCH_FSPACE as well as the plugins, since this allows the plugins to run correctly

This PR adds TRIBI to RISC-V. TRIBI 4 provides an average >3% performance improvement over MAMBO with Contiguous Traces and IHL only when running SPEC CPU 2006.

This pull request adds Contiguous Traces on top of regular RISC-V traces. This is an optimisation which reduces the critical path size and results in an average ~2.5% performance improvement...

This PR contains a number of commits which add RISC-V trace logic into MAMBO.