Jim Wilson

I posted a message to the libc-alpha thread for the 32-bit RISC-V glibc submission, to let them know about the problem. I'm not sure if there is much else I...

GDB no longer requires access to misa in order to set breakpoints. The CSR support should be working now via pull requests #160 and #182.

Perhaps there is a buffer overflow that is clobbering values on the stack. Since the problem only happens for 32-bit code, maybe the buffer overflow doesn't happen for 64-bit code....

That is a 128-bit logical right shift. But it should still be expanded inline by a 64-bit compiler. ``` rohan:2050$ cat tmp.c __uint128_t sub (__uint128_t i) { return i >>...

I can make this work with the attached patch, but I haven't convinced myself that it is correct yet. [csr-single-step.txt](https://github.com/riscv/riscv-qemu/files/2426296/csr-single-step.txt) The problem seems related to the use of DISAS_NORETURN for...

See the docs on the main-history branch. Looks like there was a major change in May that replaced the old riscv-bitmanip tree with a new one, and the new one...

Only zba, zbb, zbc, and zbs are going through the ratification process at the moment. The other extensions like zbt may be ratified in the future, but there is no...

The encodings for min/max changed recently, and no one is actively maintaining this binutils port. There are also multiple insns in the process of being added and removed. There are...

This was fixed by riscv-binutils-gdb pull request #241. So is fixed on riscv-binutils-2.35-rvb branch.

There is a closely related problem with implied extensions. D implies F, and F implies Zicsr, so if someone specifies d2p2 what if anything does that imply about the f...