openofdm Simulation of full HDL

Simulation of full HDL

Open hyanki opened this issue 4 years ago • 3 comments

Hi i have doubt that can i simulate complete design on modelsim? regards hyanki

Jun 09 '20 07:06 hyanki

Hi jshi what are the steps to simulate in icarus verilog. Regards Hyanki

Jun 10 '20 07:06 hyanki

Hi i In demodulater.v file why scaling factor is taken 1024 though input is in 16 bit? What is data format of IQ in 16bit? Regards J S Hyanki

Jul 23 '20 14:07 hyanki

if you like, you can simulate via Vivado. our reference: https://github.com/open-sdr/openwifi-hw/issues/17

Jul 23 '20 14:07 JiaoXianjun