Jordan Hand

Hey @leongross. No, I don't think anyone is actively working on this. It would definitely be nice to clean this up if you want to pick it up.

Currently RT implements its own mailbox driver: https://github.com/chipsalliance/caliptra-sw/blob/main/runtime/src/mailbox.rs. It might be preferable to use the driver that ROM uses instead: https://github.com/chipsalliance/caliptra-sw/blob/main/drivers/src/mailbox.rs One reason to maybe not do this though: RT...

Huh. CI failure looks like a flaky infra issue. Trying again. ``` E: Could not get lock /var/lib/dpkg/lock-frontend. It is held by process 3475 (apt-get) E: Unable to acquire the...

> > > Huh. CI failure looks like a flaky infra issue. Trying again. > > > ``` > > > E: Could not get lock /var/lib/dpkg/lock-frontend. It is held...

@kgugala would you be able to help debug this isse we're seeing with on VeeR (on FPGA) when existing sleep states?

Once we address this, should we enable clock gating in the CI FPGA bitstreams to make sure all the tests run against this fix?

Low priority, just wanted to make a note of it.

> Oh. Seems I just removed "fuzzing: Fix undefined symbol: cfi_panic_handler" by force pushing. Should we have a separate PR for that, or should I pull that into my repo?...

I was able to repro this on my local FPGA setup. Some additional details: * Specifically, it looks like taking a PCR quote causes subsequent PCR extensions to extend the...

I was also able to reproduce this bug on verilator (took about 4 hours to run the test): ``` 56,831,984 UART: Error: panicked at 'assertion failed: `(left == right)` 56,834,779...