armv8_pmu_cycle_counter_el0
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ARMv8 performance monitor from userspace
https://github.com/jerinjacobk/armv8_pmu_cycle_counter_el0/blob/bae0771e2551f66a7bff964bec158b18b0fcd2d4/pmu_el0_cycle_counter.c#L95
I have solve #10 after reading tips from https://github.com/rdolbeau/enable_arm_pmu/blob/master/README.md.  What I want to know is does PMCCNTR_EL0 register being shared with each cpu core and will increment it self...
@jerinjacobk I have cross-compiled your provided kernel-space code, and insmod it on my develop board, but I still got "illegal instruction", How could I fix it ? I have typed...
I try to read from the `/dev/pmuctl` deivce with `cat`, but it do NOT work. ``` bash $ cat /dev/pmuctl cat: /dev/pmuctl: Argument list too long ``` I also try...
How to read L1-dcache-misses in this project?
There is not target for modules