MAX1000 SDRAM Controller - 100 MHz and Initialization Refresh Cycles

[hemanthmab]

According to the W9864G6JT document:

An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation.

I have been using the DRAM controller with the below settings, modifying your example:

at 100 MHz Clock, for both NIOS II and SDRAM (with the SDRAM CLK having a phase shift of-3ns). Both generated by the PLL. I haven't tested it too much other than writing the whole memory area reading the values back (after calling the alt_dcache_flush_all() function). Did you experience any issues running the DRAM Controller at 100 MHz or was it because other external peripherals don't support it?

Thanks for the qsys file too, helped me understand the controller config a little bit better.