Jeff DiCorpo comments

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                                            Jeff DiCorpo

Several projects where the defaults block layout was incorrect although it had the same default block numbers.

new gpio check from Mitch should check gds. also need to roll change to script to delete previous default blocks.

add checks to tapeout flow ensure each of the steps has completed successfully

does an error with any of the steps stop the flow and generate an error?

Verilog and layout for Caravel Openframe

Yes - thanks Tim. Ping me when ready and I will merge right away. -- Jeff On Mon, May 8, 2023 at 12:51 PM R. Timothy Edwards ***@***.***> wrote: >...

LVS error with default user_proj_example

Need to confirm if this error still exists with the current version of netgen. @proppy

change pin_config to use def template for gf180

Needs review

add obstruction layers to user_project_wrapper to prevent router from using the area checked by xor

@mattvenn is this still an issue?

add obstruction layers to user_project_wrapper to prevent router from using the area checked by xor

@kareefardi review current user_project_wrapper to see if this is still an issue.

add obstruction layers to user_project_wrapper to prevent router from using the area checked by xor

If congested - there were cases where openlane was routing outside the PR boundary. @marwaneltoukhy @kareefardi please review and close if no longer an issue.

add obstruction layers to user_project_wrapper to prevent router from using the area checked by xor

suspect design to check https://www.zerotoasiccourse.com/post/mpw2-submitted/

Add additional env parameters

@marwaneltoukhy can you please review? looks like there are now conflicts due to other PR's that were merged.