Improve code generation for RISC-V

[eponier]

Btw, there is something to be checked about RISC-V, related to the linearization_params. The code was copied from arm, and it should work. But if I'm not mistaken, there are two constraints on ARM that make the code more complex:

1. there are some operations that we cannot do directly on RSP
2. instructions do not accept large immediate.

For RISC-V, 2. is true, but 1. is not. Does this mean we should adapt a bit the code?

Originally posted by @eponier in https://github.com/jasmin-lang/jasmin/issues/939#issuecomment-2434761855

[eponier]

I discussed with @bgregoir, the code of set_up_sp_register should indeed be changed into sth looking more like x86.