Subject: [PATCH] [Modified]: PLL(rcc): PCLK1 setting issue.

[dinau]

 Omit ppre1_bit selection value [1 => 0b011] and
 modify default value to "0b100",
 because when ppre_bit value is 0b011,
 ppre1 = 1 << ( 0b011-0b011) = 1,
 pclk1 = hclk / ppre1,
 pclk1 = hclk,
 if hclk is over 32MHz with PLL,
 pclk1 would be over its limit value: 32MHz.

[japaric]

Thanks for the PR, @dinau.

I would prefer not to merge this PR. When no configuration is specified everything follows the default / reset values. With this PR only ppre1 would use a non default value, wihich seems inconsistent. I think what should definitively be added is documentation about what the default values are and what the maximum allowed values are.