Add + as an argument indicator

[amal-khailtash]

Although not a standard way and rarely seen, but some tools (Verilog simulators, UVM, ...) use + to indicate custom arguments. Examples are:

+TEST=AXI_TEST
+UVM_TESTNAME=read_modify_write_test
+UVM_MAX_QUIT_COUNT=5,NO
+UVM_TIMEOUT=200000,NO
+UVM_PHASE_TRACE

This would be a great addition.