Jamey Hicks

There a bluesim-specific example of this in example/simplelink 2bddf069beb291df61e833fdea024a2fb4061c3c

Larry found a reference to partgen, but that was part of the old tool suite. The Vivado migration guide points to some tcl commands that look interesting: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_3/ug911-vivado-migration.pdf

It's true the format is very goofy. I think if we can write a short tcl script that uses Xilinx's parser for their package files it would be better.

With your Bluesim patch, you can verify that everything in mkConnectalTop for your design works with DataBusWidth=256. Working out from there, I would make a test bench that you can...

I'll review Shuotao's branch and see if I can merge it in. I'll also look at my databuswidth256 branch for relevant changes. On Wed, Nov 10, 2021 at 11:54 AM...

Please try this branch: https://github.com/cambridgehackers/connectal/pull/187 @RadhikaG I could add you as a reviewer if you like.

I haven't looked at the file, but probably should be using https://github.com/GaloisInc/BESSPIN-BSC/blob/master/src/lib/BSVSource/Xilinx/XilinxVirtexUltraScalePCIE.bsv on UltraScale devices.

@NP95 did you have any luck with the DE5 board?

Please try `lspci` to list all the PCIe devices.

To answer an earlier question, the FPGA gets programmed when you run make run.kc705g2. However, I am glad that you tried manual programming to verify that it was programmed before...