Jamey Hicks

Commit 9b40d042358a4a197d65aced8f3cc50f845b621a generates IP cores if the project has synth-ip.tcl. Commit f2717e9e97939896fdaebbb08366ea84c2d17814 fixes the problem where transferLen was set to zero because I divided by the wrong number. But it...

That version runs but there is still a problem -- it looks to me like the sync fifos are not behaving properly. Either the constraints in pcie-clocks.xdc are not correct...

I'm tracing the addresses and the output of awfifo is skipping addresses I expect to see.

I tried to have a fully script solution to incorporate the ILA but so far have not succeeded. Here is the process for nfsume: make build.nfsume When it has written...

In commit c30c8824c95a53264c5af7f1bac2c014f4d710aa I replaced mkSyncFIFO with mkDualClockFifo, my own import BVI wrapper for Xilinx's FIFO18. That improved the situation. I reconfigured the gearboxes so both ends were on the...

Looks that way. Time to work on the documentation.

I dusted off the code so I can at least regenerate documentation, now to fix that example.

I guess it would be less Jaclyn if bsvpreprocess returned a list of included files as well as the expanded source code. Do you have time to make that change?...

autocorrect strikes again :)

In case you did not see the comments I made in one of the chat channels: I think this is an artifact of the interaction between bsvpreprocess and bsvdepend. It's...