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jameslzhu
An unofficial assembly reference for RISC-V.
You are missing at least the `C.FLW`, `C.FLD`, `C.FSW`, `C.FSD` instructions.
Per ISA spec: **FNMSUB.S** multiplies the values in rs1 and rs2, negates the product, **adds** the value in rs3, and writes the final result to rd. FNMSUB.S computes -(rs1×rs2)+rs3. **FNMADD.S**...
Is this note correct? I believe the immediate field is *sign* extended (not zero extended) and then is treated (along with rs1) as an unsigned value for the comparison. See...
Is this note correct? Both source operands are registers. What is being zero-extended? The < comparison is treating both operands as unsigned but nothing is being sign-extended or zero-extended.
The text in "Shift Right Arith*" has an asterisk with no apparent purpose.
I believe the fence instruction is missing from RV32I. Only fence.i was evicted from RV32I and sent as a loner to the Zifencei extension.
Two mnemonic in RV23M seem mispelled: - "mulu" should be "mulhu" - "mulsu" should be "mulhsu"
@esmil The Notes column, the first two "zero-extends" comments are mis-placed. They should be beside the Logical Shift Right commands, not the Set Less Than instructions. @
