Fix#45 afonly

[RGD2]

This just changes the uarrt's rx inpin to async_in_filter.

This protects the buart input from metastability and glitches on the rx input, which seems to fix #45. And is likely to increase reliability whenever the buart is connected to an asynchronously-clocked serial signal. (ie, with icepll settings other than 12 or 48 MHz).

async_in_filter is a good way to implement slow asynchronous inputs, which may otherwise suffer from metastability or glitches.

It's useful as a switch de-bouncer with larger FILTERBITS settings like so:

async_in_filter #(.FILTERBITS(11)) _myinpin(.clk(clk), .pin(somepin), .rd(myinput));

It adds a delay, but will prevent oscillations with periods less than 2^(FILTERBITS-1) clks. Total delay to an isolated pulse should be 3+(3/4)*2^(FILTERBITS) clks.

5 bits is good for a 1 MHz square wave, when used with a 48 MHz system clk, and is the default setting.