spi-fpga
spi-fpga copied to clipboard
jakubcabal
Maximum SCLK frequency on SPI SLAVE module
Hi, firstly your code is very clear and i'm learning a lot from this, so thanks!
Then I was reading in another issue that with a CLK frequency that is at least twice the SCLK frequency the code works fine.
I was trying to use a CLK at 12 MHz and a SCLK at 4 MHz and i found some problem with the MISO of the SPI SLAVE module. Pratically the first 1 sended on the MISO remains too much on it and is sampled two times.
I'm using a simplified testbench that i can attach here.
There is something that I can do to fix this problem?
Another problem that can be seen in the snapshot is that when I send the next code, the MOSI switch correctly but the MISO is sending the previous code. In the shift register infact there is the old code. Am I doing something wrong in the testbench?
From the readme, SCLK must be <= CLK/10:
With a 12MHz input clock, the maximum SCLK you can safely define is 12MHz/10 = 1.2MHz. If you need the 4MHz SCLK then you'll need a faster input clock
(I literally just found this project and I'm not familiar with the code, just referencing the documentation)
