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verified publisher icon j-marjanovic

Illegal routes

Open Nic30 opened this issue 3 years ago • 0 comments

I am using Quartus 18.0 I did successfully generated bitstream, I used https://gist.github.com/wirebond/9e75db58112bb49c6b2debad7dc13cb2 to enable second HIP and I can see it used in Chip Planer.

Everything seems fine however there are two routes with status illegal.

inst_system|pcie1|altera_s5_a2p|altpcie_hip_256_pipen1b|g_xcvr.sv_xcvr_pipe_native|inst_sv_xcvr_native|inst_sv_pcs|ch[4].inst_sv_pcs_ch|inst_sv_hssi_8g_rx_pcs|wys|clocktopld	inst_system|pcie1|altera_s5_a2p|altpcie_hip_256_pipen1b|g_xcvr.sv_xcvr_pipe_native|inst_sv_xcvr_native|inst_sv_pcs|ch[4].inst_sv_pcs_ch|inst_sv_hssi_8g_rx_pcs|wys|clocktopld	Generated	Illegal
inst_system|pcie1|altera_s5_a2p|altpcie_hip_256_pipen1b|g_xcvr.sv_xcvr_pipe_native|inst_sv_xcvr_native|inst_sv_pcs|ch[4].inst_sv_pcs_ch|inst_sv_hssi_8g_rx_pcs|wys|observablebyteserdesclock	inst_system|pcie1|altera_s5_a2p|altpcie_hip_256_pipen1b|g_xcvr.sv_xcvr_pipe_native|inst_sv_xcvr_native|inst_sv_pcs|ch[4].inst_sv_pcs_ch|inst_sv_hssi_8g_rx_pcs|wys|observablebyteserdesclock	Generated	Illegal

Is this expected?

Nic30 avatar Mar 27 '22 09:03 Nic30