Ivan Rusanov

@roman-orekhov Build is up, contains all the latest changes. https://github.com/irusanov/SMUDebugTool/releases/tag/v1.3.0-beta Let me know if something doesn't work as expected.

@PJVol That feature isn't perfect, since it's only reading the SMU addresses at a given interval in an attempt to detect a change, but the readings might be out of...

I'm testing on a X370 chipset (Crosshair VI Hero). I also have a B350 spare board (Asrock B350 K4) and will try soon. The CH6 does not have VGA output,...

> Yeah, but understanding the bit fields for some command is not that easy. I figured out arg bit layout for the setting psm margins per core dLDO. If you...

There should be a way to override this, since it's possible from bios, but I'm not sure it could be done runtime. I'm not able to switch to OC mode...

It seems RavenRidge responds to P-States only. To get above turbo frequency, you need to change P-State0 DID to something lower than what is detected as stock. Then you can...

@PJVol How so? Reading the address on my 3900X gives me 0x0000001110001000, where 1 means "disabled" core. Or if we divide them into CCDs -> [00000011] [10001000] This means, if...

@PJVol Thanks for the heads up, should be now fixed in core DLL.

> @irusanov If you disable one of the CCDs in BIOS, what would that higher byte read? Still 0b00000011 for both? Thought about that and will have to check, it...

@roman-orekhov, @patrickschur It's been referenced as "cac counters" in uProf UserGuide and IOMMU specification: [AMDuProf User Guide](https://developer.amd.com/wordpress/media/files/AMDuprof_Resources/User_Guide_AMD_uProf_v3.2_GA.pdf) (page 53) [AMD I/O Virtualization Technology (IOMMU) Specification, 48882](https://www.amd.com/system/files/TechDocs/48882_IOMMU.pdf) The IOMMU document has...