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This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

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Hello, I am trying to integrate your project in my Systemc-UVM testbench. I have run into few things that are missing for me, or I dont know how to write...

**Hierarchy:** ---------- TOP --> TB --> DUT **DUT module:** ----------- sc_port< tlm_nonblocking_get_peek_if< bool > > status; ... if (status->nb_can_get()) { bool status_in; status->nb_get(status_in); } **TB module:** ---------- sc_port< tlm_nonblocking_put_if< bool...

Error with ibm128 type -- needs to debug it