Support negative edge-triggered `Sequential`s

[mkorbel1]

Description & Motivation

Adds support for negative edge-triggered Sequentials. In some cases, downstream tools may treat an inverted clock fed into a sequential differently than a negative edge triggered sequential. Functionally, in simulation, the behavior is the same for either option. Generators may choose to generate these differently (e.g. using negedge vs. posedge in SystemVerilog generation).

Additionally fixed a bug where a multi-triggered Sequential may not generate X's if one trigger is valid and another (later specified) trigger is invalid.

The changes also motivated some refactoring of trigger handling in Sequential, as well as renaming of the first positional argument in Sequential.multi.

Related Issue(s)

This is related to the discussion on #42, where previously it was decided not to include negedge due to lack of motivation. Downstream tool differences now motivate adding the feature.

Testing

Added new tests, existing tests pass.

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No, but the signature of Sequential.multi has been slightly expanded and modified:

• first positional argument changed name from clks to posedgeTriggers
• added negedgeTriggers as a named optional argument

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

This is a relatively uncommon feature, so documentation added onto the API docs should be sufficient (extra example in user guide not really needed).