Make full array assignments compressed to 1 line (or in-lined) in generated SystemVerilog

[mkorbel1]

Motivation

For compatibility purposes, ROHD currently does per-element assignments between arrays. A common case of assignment between two entire arrays of the same dimensions makes many more lines than is necessary. This makes the generated SV more verbose than it needs to be.

Desired solution

Intelligently compress assignments between arrays with the same dimensions to a single-line assignment.

Alternatives considered

No response

Additional details

This is not a functional change, just makes the generated SV nicer.