Improve lint avoidance for width expansion

[mkorbel1]

Motivation

The current implementation (https://github.com/intel/rohd/issues/298, https://github.com/intel/rohd/pull/423) for handling width expansion (e.g. from adding, shift left, multiplication, etc.) avoids lint errors successfully, but still hits some lint warnings and is also somewhat ugly.

A nicer way to generate it might look something like this:

assign {cout, out} = a + b + cin;

Desired solution

Upgrade modules to generate prettier SV that avoids both lint errors and warnings

Alternatives considered

No response

Additional details

No response

[mkorbel1]

We should investigate free/open-source linting tools for checking and CI flows to help catch issues and prevent regressions. Perhaps verilator's linting can help? https://projectf.io/posts/verilog-lint-with-verilator/

[mkorbel1]

Another open-source linter: https://github.com/dalance/svlint