Feature to store `WaveDumper` output in memory

[chykon]

Motivation

Since ROHD has become a DartPad-supported package, it might be worth considering playground limitations. Attempting to use WaveDumper results in an error because the ability to save files is not available.

Desired solution

Add the ability to store the output of WaveDumper in memory. Further, the user can do, for example, print at will (as with the generated SystemVerilog code).

Alternatives considered

No response

Additional details

I understand that for large projects, large vcds can be generated that can take up all the memory if they are not flushed to disk. But it is acceptable for small projects/examples.

[mkorbel1]

Something like this has actually been on my mind for another purpose as well: easier debug and hooks for debug tools. I was considering if there should be a way for each individual Logic to store its entire history itself rather than centrally storing it in the WaveDumper. This has a couple cool benefits:

• When you hit a breakpoint in the simulation, you can immediately see in the debugger the history of values of that signal
• If we create a vscode extension or something else that plugs into the Dart debugger, the tool can view signal history and provide additional insight. For example, a ROHD waveform viewer plugin could leverage this.

The memory size concern is real for big designs. Though the size in memory of this history could likely be much smaller than the VCD size since the variables to store LogicValue and Simulator.time take up less space than the equivalent number of characters in an uncompressed text file like VCD. It might be viable for bigger designs than one would expect.